1. Field of the Invention
Generally, the present disclosure relates to the field of fabrication of integrated circuits, and, more particularly, to the patterning of lines, such as gate electrodes, of field effect transistor devices on the basis of a mask layer, such as a resist mask.
2. Description of the Related Art
In modern ultra-high density integrated circuits, device features are steadily decreased to enhance device performance and functionality. One important circuit element in complex integrated circuits is a field effect transistor, which represents a component having a channel region, whose conductivity may be controlled by an electric field that is generated by applying a control voltage to a gate electrode formed near the channel region and separated therefrom by a gate insulation layer. The channel region is generally defined by respective PN junctions formed by an interface of highly doped drain and source regions and an inversely doped region located between the drain and source regions. Important characteristics for the performance of an integrated circuit are, among others, the switching speed of the individual transistor elements and the drive current capability. Thus, one important aspect for obtaining a high transistor performance is the reduction of the overall resistance of the current path defined by the channel region, the resistance of the drain and source regions and the respective contacts that connect the transistor with peripheral devices, such as other transistors, capacitors and the like. The reduction of the channel length thus provides reduced resistance of the channel region and also offers the potential to increase the packing density of the integrated circuit. Upon reducing the transistor dimension, the transistor width is also typically reduced in view of packing density and switching speed, which may, however, reduce the drive current capability. It is therefore of great importance to reduce the series resistance of a transistor for given design dimensions as much as possible so as to combine moderately high drive current capability with increased switching speed for sophisticated logic circuits.
As previously explained, the channel length and the channel width are critical parameters for the performance of a specified field effect transistor. With reference to FIGS. 1a-1c, a typical conventional process flow will now be described in more detail in order to more clearly demonstrate the problems associated with the patterning of a gate electrode of highly advanced transistor elements.
FIG. 1a schematically illustrates a semiconductor device 100 in a top view, which comprises a substrate 101, which may have formed thereon any appropriate semiconductor material, such as silicon and the like. A trench isolation structure 102 is formed in the substrate 101, i.e., in the respective semiconductor layer so as to define a first active semiconductor region 110 and a second active semiconductor region 120. It should be appreciated that the term “active semiconductor region” is to be understood as describing a semiconductor area including certain dopants, at least in certain portions of the active region, in order to provide a desired conductivity of the region. The first and second active semiconductor regions 110, 120 may substantially represent a respective semiconductor area, in which respective drain and source regions as well as channel regions of a transistor have been formed or will be formed. Furthermore, a first gate electrode 111 is formed above the first active semiconductor region 110 and extends, at least according to the design requirements, with an end portion 111e over the trench isolation 102. Similarly, a second gate electrode 121 is formed above the second active semiconductor region 120 and extends with a respective end portion 121e partially over the trench isolation 102.
FIG. 1b schematically illustrates a sectional view as indicated in FIG. 1a of the semiconductor device 100 at an early manufacturing stage for forming the first and second gate electrodes 111, 121. As illustrated, the device 100 comprises the trench isolation 102 separating the respective active regions 110 and 120. Moreover, a gate electrode material 103 may be formed above the regions 110, 120 and the trench isolation 102, wherein a gate insulation layer 104 is provided between the gate electrode material 103 and the respective active regions 110, 120. Furthermore, in this manufacturing stage, respective resist features 115 and 125 may be formed above the first and second active regions 110, 120, respectively, wherein the respective resist features 115, 125 may be separated by a spacing 130. Furthermore, as is illustrated, an anti-reflective coating (ARC) 106 may be formed between the gate electrode material 103 and the respective resist features 115, 125. It should be appreciated that, in the manufacturing stage shown in FIG. 1b, the resist features 115, 125 may be similar to the respective gate electrodes 111, 121 to be formed from the gate electrode material 103, wherein, however, the respective lateral dimensions may be significantly greater compared to the actual design dimensions of the gate electrodes 111, 121. That is, typically gate electrodes and many other components of transistor elements are patterned on the basis of photolithography techniques in which a corresponding pattern is imaged from a reticle into a resist layer, which is then developed and used as an etch mask for subsequently patterning an underlying material. In sophisticated applications, typically the resolution of the photolithography process is significantly less compared to the actual target dimensions of critical features, such as the gate electrodes 111, 121. For example, in highly sophisticated photolithography techniques, an actual dimension, for instance a width of a line feature, may range between approximately 90-100 nm, while the actual target dimension for a correspondingly patterned line feature may be 60 nm or even less. Consequently, a further reduction in size of the resist features 115, 125 may be necessary, as will be explained later on.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1b may comprise the following processes. After forming the respective trench isolations 102 on the basis of well-established photolithography, etch, deposition and planarization techniques, the gate insulation layer 104 may be formed on the basis of established oxidation and/or deposition processes. For instance, silicon dioxide, possibly in combination with silicon nitride, are frequently used dielectric materials for advanced field effect transistors, wherein a thickness may range from approximately 1.5-5.0 or more nm, depending on design and device requirements. Thereafter, the gate electrode material 103, typically polysilicon, may be deposited on the basis of well-established low pressure chemical vapor deposition (CVD) techniques, wherein a thickness of the material 103 may range from approximately 80-150 nm for devices of the above-specified critical dimensions. Thereafter, the ARC layer 106 may be formed, for instance by well-established plasma enhanced or thermal CVD techniques, followed by the deposition of any appropriate resist material, selected on the basis of the exposure wavelength used during the subsequent photolithography process. Next, the resist material may be treated in accordance with well-established recipes and may be exposed in order to form a respective exposure pattern in the resist layer that substantially corresponds to the respective circuit features to be formed from the layer 103, except for the lateral dimensions. After the photolithography process, which may comprise additional bake and other post-exposure process steps, the semiconductor device 100 as shown in FIG. 1b may be subjected to a further trim process in order to reduce the size of the resist features 115, 125 resulting from the previous photolithography process.
FIG. 1c schematically illustrates the semiconductor device 100 during a resist trim process 107, which is designed to reduce the lateral dimensions of the resist features 115, 125 in accordance with process requirements so as to obtain reduced features 115R, 125R which may then serve as etch masks for patterning the gate electrode material 103. The trim process 107 is designed as an isotropic etch process, for instance on the basis of oxygen including a plurality of halides and/or fluorine, since oxygen may provide a highly isotropic behavior for a plurality of polymer materials. Thus, the length and width and, due to the isotropic nature of the process 107, the height of the initial features 115, 125 may be significantly reduced in order to obtain the desired target values for the length and width of the reduced features 115R, 125R. Consequently, during the trim process 107, the initial spacing 130 is also significantly increased, as is indicated by 130R. It should be appreciated that the transistor width direction in FIG. 1c corresponds to the horizontal direction, indicated as W, while the transistor length direction is substantially perpendicular to the drawing plane of FIG. 1c. Hence, an increase of the spacing 130R represents a reduction in width of the respective features 115R, 125R, and a reduction in size in the direction perpendicular to the drawing plane corresponds to a reduction of the gate length.
After the resist trim process 107, an anisotropic etch process may be performed in order to transfer the size and shape of the resist features 115R, 125R into the underlying layers 106 and 103. For example, when polysilicon is used, a plasma-based etch process using chlorine, hydrogen bromide and oxygen as reactive gases may be employed. Depending on the characteristics of the respective etch process, a further reduction in size of the resist features 115R, 125R may result and may therefore also reduce the etch fidelity, which may possibly result in reduced overlap of the respective gate electrodes and the trench isolation 102, which may be undesirable with respect to transistor performance.
FIG. 1d schematically illustrates the semiconductor device 100 after the corresponding anisotropic etch process, thereby forming the first and second gate electrodes 111, 121. As is well known, the gate electrode of a field effect transistor may control the conductivity of a respective channel region 113, 123 that forms below the gate insulation layer 104 upon application of an appropriate control voltage to the respective gate electrodes 111, 121. In the sectional view, the flow direction of charge carriers within the channel regions 113, 123 is substantially perpendicular to the drawing plane, while the horizontal extension of the respective channel regions 113, 123 corresponds to the width of the respective channels. Hence, for a specified channel length and for otherwise identical transistor configurations, an increased channel width may result in an increased drive current capability. Consequently, for a given transistor configuration, it is important for optimizing transistor performance to substantially completely “use” the available channel region, which may also require an appropriate electric field at edge regions 124, 114 of the respective channel regions 113, 123.
As is illustratively shown in FIG. 1d, the gate electrode 121, due to tolerances of the preceding patterning process, may have substantially no overlap at the edge region 124, while the gate electrode 111 may have an appropriate overlap with the isolation trench 102, which may be advantageous with respect to the creation of an appropriate electric field at the edge region 114. Consequently, during operation, substantially the whole channel 113 including the edge region 114 is available for charge carrier transport, while a sufficient electrical field for building up a conductive channel at the edge region 124 in the channel region 123 may be reduced. Consequently, reduced transistor performance may result from a non-overlapping gate electrode. As is shown in FIG. 1c, reducing the initial spacing 130, which may be advantageous with respect to transistor performance, may be less than desirable in the conventional process flow, since the resist trim process 107 may then result in respective resist residues in the spacing 130R, which may in turn yield respective residues of the polysilicon material 103, thereby possibly forming a short circuit between the gate electrodes 111 and 121. Consequently, in the conventional gate patterning process as previously described, a compromise is to be made between a desired overlap of the gate electrode with the isolation structure and the avoidance of any short circuits between adjacent opposing end portions, which are also referred to as end caps, of different gate electrodes.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.